The present invention relates generally to the field of frequency synthesizers. More specifically, the present invention relates to frequency synthesizers which incorporate a phase-locked loop to generate an output frequency and which are prepositioned so as to quickly settle at new frequencies while experiencing low phase noise.
In frequency hopping radios and other applications a need exists for synthesizing a variety of frequencies with low phase noise and with the ability to quickly settle at new frequencies. A direct synthesis technique uses algebraic manipulation of one or more reference frequencies to produce output frequencies. While direct synthesis may be configured to exhibit quick settling and low phase noise, it unfortunately suffers from a limited bandwidth and often requires complex and expensive filtering.
A more common approach to the frequency synthesizing needs of frequency hopping radios and other applications employs an indirect technique relying on a programmable phase-locked loop (PLL) to control a voltage controlled oscillator (VCO) that produces desired-output frequencies. A conventional, non-prepositioned PLL-type frequency synthesizer includes a phase comparator, loop filter, VCO, and frequency divider all arranged in a loop, and a reference frequency source. The frequency divider is programmed to achieve a desired output frequency at the VCO. The phase comparator compares phases of a reference frequency and a divided output frequency. The loop filter responds to the phase comparator and drives the VCO to alter its output frequency in a manner that reduces phase differences at the phase comparator. This indirect, non-prepositioned technique can provide a low cost, wide bandwidth synthesizer. Unfortunately, it achieves low phase noise using a narrow bandwidth loop filter that causes slow settling to new frequencies, or achieves quick settling to new frequencies using a wide bandwidth loop filter that causes high phase noise.
Accordingly, conventional PLL-type frequency synthesizers have devised prepositioning techniques that seek to establish certain initial conditions in the PLL when switching to new frequencies. In other words, indirect, prepositioned frequency synthesizers xe2x80x9cprepositionxe2x80x9d a PLL, which typically has a narrow bandwidth loop filter, to an initial condition from which the PLL need not search very far in order to achieve a condition where the output frequency is locked to a reference frequency. Since the PLL need not search far to achieve lock, it settles at new output frequencies more quickly than a non-prepositioned PLL-type frequency synthesizer having about the same loop-filter bandwidth.
In one form of conventional prepositioning, the voltage stored on a loop-filter capacitor is prepositioned to approximately that voltage expected when the desired output frequency is generated. The more accurate forms record the capacitor voltage during an earlier period when a given output frequency has been generated, then attempt to set the capacitor voltage to that same value at the beginning of a later period when the same frequency is to be generated again. But capacitor voltage is a sensitive parameter where small errors can lead to large output frequency offsets. Even the more accurate forms of this type of prepositioning fail to accurately set the capacitor to the correct voltage; the PLL""s are then forced to expend precious time searching for desired output frequencies; and, settling time suffers.
In another form of conventional prepositioning, the frequency divider is prepositioned to an initial condition where the divided output frequency is phase matched, at least at a given instant, with the reference frequency. This type of prepositioning prevents a phase rollover phenomenon that can be responsible for a PLL experiencing a very long lock time. Phase rollover occurs when the phase of the divided output frequency is nearly 180xc2x0 out-of-phase with the reference frequency even though the frequencies may be nearly equal.
Unfortunately, the conventional approach to this type of prepositioning inserts delay into the frequency-switching process by waiting to reset a frequency divider counter until a predetermined edge of the reference signal is detected, and the delay slows the settling time. Moreover, the occurrence of the predetermined edge of the reference signal is often a time-uncertain event because the reference signal is not synchronized with the circuitry that resets the frequency divider. Accordingly, settling times can only be guaranteed for the worst case delay that might occur while waiting for the predetermined edge of the reference signal.
What is needed is a prepositioned frequency synthesizer that improves upon conventional prepositioning techniques so that faster settling times may be achieved for a given loop filter bandwidth.
It is an advantage of the present invention that an improved prepositioned frequency synthesizer and method are provided.
Another advantage of the present invention is that frequency synthesizer prepositioning techniques are improved upon to achieve faster settling times for a given loop filter bandwidth.
Another advantage of the present invention, at least in one embodiment thereof, is that a compensation circuit is provided to accurately preposition the state of a loop filter so that errors are reduced and the PLL need not search as far to settle at a desired frequency.
Another advantage of the present invention, at least in one embodiment thereof, is that frequency dividers are provided for both a reference frequency and the output frequency so that, among other reasons, both frequency dividers can be instantly set to an initial value where the signals compared in a phase comparator are nearly equal.
These and other advantages are realized in one form by an improved prepositioned frequency synthesizer for rapidly settling at new frequencies. The prepositioned synthesizer includes a first frequency divider configured to divide a frequency of a synthesizer-output signal by a number N. A second frequency divider is configured to divide a frequency of a reference signal by a number M. A phase comparator has inputs coupled to the first and second frequency dividers, and a loop filter couples to the phase comparator. A variable frequency oscillator has an input coupled to the loop filter and an output configured to provide the synthesizer-output signal. A filter-state-recording circuit couples to the loop filter and is configured to record states exhibited by the loop filter. A filter-state-assigning circuit couples to the loop filter and is configured to assign states to the loop filter. In addition, a controller couples to the first and second dividers and to the filter-state-assigning circuit. The controller is configured to set the first and second frequency dividers to initial conditions and to assign a state to the loop filter when changing to a new frequency.
These and other advantages are realized in another form by an improved prepositioned frequency synthesizer for rapidly settling at new frequencies. The prepositioned synthesizer includes a reference frequency source and a frequency divider configured to divide a frequency of a synthesizer-output signal by a number N. A phase comparator has a first input coupled to the frequency divider and a second input coupled to the reference frequency source. A loop filter couples to the phase comparator, and a variable frequency oscillator has an input coupled to the loop filter and an output configured to provide the synthesizer-output signal. A filter-state-recording circuit couples to the loop filter and is configured to record states exhibited by the loop filter. A filter-state-assigning circuit couples to the loop filter and is configured to assign states to the loop filter. In addition, a compensation circuit couples to the filter-state-recording circuit and to the filter-state-assigning circuit. The compensation circuit is configured to compensate for response differences between the filter-state-recording circuit and the filter-state-assigning circuit.